1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly, to a magnetic random access memory (MRAM) and a layout structure thereof including a write is driver.
2. Related Art
A dynamic random access memory (DRAM) operates in a relatively high operational speed with relatively low power consumption but is volatile. A flash memory is nonvolatile and can be miniaturized to a size much less than a general hard disc drive as well as made more resistant to physical impact that a hard disc drive, but a flash memory, when compared to a DRAM, operates at a lower speed while requiring a higher operational voltage.
A magnetic random access memory (MRAM) stores digital information utilizing the resistance variation related to polarity change of a magnetic substance and, because magnetism is used, exhibits better reliability.
In general, an MRAM has bit lines, word lines, and digit lines that are parallel to the word lines. An MRAM records data using a vector sum of the magnetic fields that are induced by the current flowing simultaneously through the bit lines and the digit lines. Because digit lines are additionally needed in an MRAM, it poses as a limitation to decreasing the cell size in an MRAM. Also, when recording data by selecting a cell, unselected nearby cells are likely to be exposed to the magnetic fields as well and may wrongly invert the data storage states of the unselected cells.
A spin transfer torque magnetic random access memory (STT-MRAM) is an improved variation of an MRAM.
As indicated in the name, a STT-MRAM utilizes the spin is transfer torque phenomenon that is characterized by, when a high density current having an aligned spin direction is incident on a ferromagnetic substance, the magnetization direction of the ferromagnetic substance aligning with the spin direction of current when the magnetization direction of the ferromagnetic substance does not correspond to the spin direction of current. The STT-MRAM includes one selection transistor and a magnetic tunnel junction (MTJ) which are connected between a bit line and a source line.
FIG. 1 illustrates an exemplary MTJ which is applied to an STT-MRAM generally known in the art.
As illustrated in FIG. 1, a magnetic tunnel junction 1 includes a first electrode layer as a top electrode, a second electrode layer as a bottom electrode, a first magnetic layer and a second magnetic layer as a pair of magnetic layers, and a tunneling barrier layer which is formed between the pair of magnetic layers.
The first magnetic layer may be a free ferromagnetic layer that changes a magnetization direction according to the direction of current applied to the MTJ, and the second magnetic layer may be a pinned ferromagnetic layer having a pinned magnetization direction.
The resistance change of the MTJ, which depends upon the direction of current, is utilized to record “0” or “1” information.
A data recording principle for the MTJ will be described with reference to FIGS. 2a and 2b 
With reference to FIG. 2a, a principle for recording data of a logic low level (0) in the MTJ will be described. To record data in the MJT in FIG. 2a, the word line WL is enabled, and the selection transistor ST is turned on. Then, as current flows in a direction extending from a bit line BL to a source line SL, that is, as current flows from the first electrode layer as the top electrode of the MTJ to the second electrode layer as the bottom electrode of the MTJ (as indicated by the dotted arrow in FIG. 2a), the magnetization direction of the first magnetic layer as the free ferromagnetic layer and the magnetization direction of the second magnetic layer as the pinned ferromagnetic layer become parallel to each other. As a result, a low resistant state is created, and the data at this time may be defined as having a logic low level (0).
With reference to FIG. 2b, a principle for recording data of a logic high level (1) in the MTJ will be described. Similarly, to record data in the MJT in FIG. 2b, the word line WL is enabled, and the selection transistor ST is turned on. Then, as current flows in a direction extending from the source line SL to the bit line BL, that is, as current flows from the second electrode layer to the first electrode layer (as indicated by the dotted arrow in FIG. 2b), the magnetization direction of the first magnetic layer and the magnetization direction of the second magnetic layer become anti-parallel to each other. As a result, the MTJ has a high resistant state, and the data at this time may be defined as having a logic high level (1).
FIG. 3 illustrates the structure of a cell array of an STT-MRAM generally known in the art, which records data using the bi-directional flow of current as described above with respect to FIGS. 2a-2b. 
As illustrated in FIG. 3, source lines SL0 and SL1 and bit lines BL0 and BL1 are aligned parallel to each other, and word lines WL0 and WL1 are aligned perpendicular to the source lines and the bit lines.
A pair of MTJ and selection transistor connected in series between the bit line and the source line to allow current to flow from the bit line to the source line or from the source line to the bit line, so as to record data.
FIG. 4 illustrates the cell array layout of the cell array circuit illustrated in FIG. 3.
As shown in FIG. 4, the MTJ and the selection transistor are formed in an active area 10 to connect to the bit line and the source line in series, and a word line is aligned at a gate terminal of the selection transistor.
In a STT-MRAM having the structure shown in FIG. 4, the unit cell area 12 is 12F2 (where F is the word line pitch), and there are limitations to further minimizing the unit cell area 12, mainly because the bit line and the source line are provided in each cell.
FIG. 5 is a circuit diagram of a write driver circuit for an STT-MRAM generally known in the art.
As illustrated in FIG. 5, the write driver circuit includes a first logic element ND1 receiving the inversion signal of a data signal DATA and a write enable signal WREN and outputting a low level signal when the two received signals are at a high level, and a second logic element NR1 receiving the inversion signal of the data signal DATA and the inversion signal of the write enable signal WREN and outputting a high level signal when the two received signals are at a low level.
In addition, the write driver circuit includes a first transistor P1 driven by the output signal of the first logic element ND1 and having a source terminal connected to a power supply voltage terminal VDD, and a second transistor N1 driven by the output signal of the second logic element NR1 and having a drain terminal connected to a drain terminal of the first transistor P1 and a source terminal connected to a ground voltage terminal VSS. Moreover, the write driver circuit includes a third transistor P2 driven by the inverted output signal of the second logic element NR1 and having a source terminal connected to the power supply voltage terminal VDD, and a fourth transistor N2 driven by the inverted output signal of the first logic element ND1 and having a drain terminal connected to a drain terminal of the third transistor P2 and a source terminal connected to the ground voltage terminal VSS.
In order to record data in the STT-MRAM, the write enable signal WREN is activated. When data DATA to be recorded is at a high level, since the output signal of the first logic element ND1 is at a high level and the output signal of the second logic element NR1 is at a high level, the second transistor N1 and the third transistor P2 are turned on, but the first transistor P1 and the fourth transistor N2 are turned off.
As a result, a terminal connected to the bit line BL is at a low level and a terminal connected to the source line SL is at a high level, so that current flows in the direction extending from the source line to the bit line and thus data at a high level is recorded in the MTJ.
When data DATA to be recorded is at a low level, the first transistor P1 and the fourth transistor N2 are turned on, but the third transistor P2 and the second transistor N1 are turned off, so that current flows in the direction extending from the bit line BL to the source line SL and thus data at a low level is recorded in the MTJ.
In the STT-MRAM shown in FIGS. 1-5, the bit line and the source line are aligned in each cell. Therefore, as illustrated in FIG. 4, the unit cell area is 12F2, and there are limitations to improving the degree of high integration.
In addition, the current is provided through the write driver circuit as shown in FIG. 5 to record data in each unit cell. That is, the first and second transistor elements P1 and N1 for providing the current to the bit line BL and the third and fourth transistor elements P2 and N2 for providing the current to the source line SL are necessary. Therefore, efficiency is not ensured in terms of current consumption.